Senior Engineer - Silicon Physical Design (Italy based)

Axelera AI is creating the next‑generation AI platform to support anyone who wants to help advancing humanity and improve the world around us. We have raised $120M in four years, built a world‑class team of 220+ employees, 49+ PhDs with over 40,000 citations, and maintain offices in Belgium, France, Switzerland, Italy, the UK and the Netherlands.

Position Overview

As a Senior Silicon Physical Design Engineer at Axelera AI, you will develop multi‑core in‑memory compute SoCs, handling ASIC Physical Design from RTL to GDS. Your responsibilities include synthesis, floorplanning, place and route, extraction, timing analysis, physical verification, EMIR sign‑off, and formal verification. You will work closely with architecture and RTL teams to ensure successful project execution.

Key Responsibilities

• Perform synthesis, floorplanning, place and route, extraction, timing analysis, and physical verification.
• Ensure timing closure, constraint generation, and optimization.
• Execute clock tree synthesis (CTS) and clock‑building techniques.
• Integrate IPs including memories, I/Os, embedded processors, DDR, networking fabrics, and analog IPs.
• Utilize EDA tools such as Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, and Calibre.
• Develop automation scripts in Python, Tcl, or Perl.
• Debug and solve technical challenges related to physical design.
• Collaborate with architecture, RTL, and verification teams.

Qualifications

• 10+ years of experience in Physical Design (RTL to GDS).
• Strong communication and teamwork skills.
• Expertise in synthesis, timing analysis, and timing closure.
• Hands‑on experience with leading EDA tools (Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, Redhawk, and Calibre).
• Proficiency in clocking techniques and CTS.
• Experience in IP integration across various domains.
• Strong scripting skills (Python, Tcl, or Perl).
• Proven problem‑solving and debugging capabilities.
• Fluent in English (spoken and written). Italian not required.

Highly Preferred

• Experience in top‑level integration and I/O ring design.
• Knowledge of chip‑package‑board co‑simulation and packaging.
• Ability to influence design methodologies and tool flows.
• Experience working with EDA vendors to resolve tool issues.
• Understanding of semiconductor device physics and multi‑domain design.

Location

This position is based in Italy (hybrid or remote setup). Axelera AI supports relocation to Bologna, Florence or Milan for talented individuals abroad who are interested in this role.

What We Offer

You will shape and be part of a dynamic, fast‑growing, international organization. Compensation includes an attractive package, pension plan, extensive employee insurances, and the option to receive company shares. We foster an open culture that supports creativity and continual innovation, with collaborative ownership and freedom with responsibility.

Equal Opportunity Statement

Axelera AI wholeheartedly embraces equal opportunity and holds diversity in the highest regard. We welcome applicants from all backgrounds to join us in shaping the future of AI.