Functieomschrijving

Bedrijfsomschrijving

The sector Development & Engineering (D&E) of ASML is responsible for the specification, design and realization of the products in the ASML portfolio.

Within the sector D&E the department Electronic Development (EDEV) is responsible for the definition, realization, qualification and integration of all electronic functions and modules within these products.

Within EDEV the group Embedded Computing Engineering (ECE) is responsible for the Embedded Computing Solutions for EDEV and connected to the Motion Control Release Train. The GDB team is part of the ECE group and responsible for the development and maintenance of generic FPGA IP blocks (including HW) for all ASML PCBA and FPGA designs.

As a Verification Engineer in the Generic Design Blocks (GDB) team you are responsible for the following:

• Act as the EDEV representative in a multidisciplinary design team.
• Interact intensively with colleagues from the software & hardware department.
• Define, document and maintain requirements of various IP's (firmware GBD's).
• Define, document, and execute tests to ensure that the firmware satisfy the requirements.
• Perform trade-off studies to determine the preferred implementation scenario for new or changed functions. Get agreement with stakeholders.
• Contribute to GDB roadmap and building-blocks. COTS solutions and using industry standards are highly preferred.
• Make work breakdown and planning for the various firmware products, adjusted with other stakeholders.
• Analyze and solve GDB design issues.

The FPGA Verification Engineer will report to the team leader of the GDB team.

Educational and experience

• Bachelor- or Master Degree in Electrical Engineering or Computer Science.
• 3+ years of experience as a Verification Engineer with FPGA's or equivalent is a must have.
• Extensive experience with System Verilog and UVM is a must have
• Understanding of VHDL / Verilog Designs is a must have.
• Experience with Assertion Based Verification (SVA especially, PSL) is preferred
• Broad technical knowledge of digital IP's (Firmware building-blocks) is preferred.
• Experience with Altera / Xilinx Design Flow is preferred.

• A 13th-month payment, pro-rated periodically
• 8.33% holiday allowance calculated on 12 monthly salaries
• Pension Plus scheme (build-up from day 1)
• 25 vacation days per year based on a 40-hour work week
• Various allowances (travel, internet, home working)